Summary: ECP5 SerDes Out-Of-Band Tx/Rx

Mon, 14 Sep 2020 10:04:21 -0600

This post is a summary of the findings from my look at using the ECP5 SerDes for USB3 LFPS for quick reference of how to use the ECP5 SerDes semi-documented out-of-band I/O features.

Quick summary:

In addition to using the ECP5’s SerDes pins to drive the SerDes; the SerDes Tx/Rx pins can also be used as Low-Data-Rate (LDR) outputs/inputs while the SerDes is in use.
This is intended to allow transmission/receipt of out-of-band signals in addition to normal SerDes operation; and thus requires a configured SerDes.

Documentation

To use this functionality, add the following to the invocation of the SerDES DCUA block, replacing CHX with your channel number:

USB3 LFPS Using ECP5 SerDes I/O

Tue, 01 Sep 2020 11:38:10 -0600

Lately, I’ve been developing a USB3 stack, and a USB3 frontend using the ECP5 SerDes. The ECP5 SerDes seems almost perfect for USB3, which shares many of its implementation details with PCIe. However, there are a couple of hitches.

The more difficult to deal with is support for USB3’s Low Frequency Periodic Signaling (LFPS). LFPS carries small bursts of information via a slow, out-of-band signal, meant to be used before the high-speed USB3 link is established:

Ecp5 on kate's lab notebook

Summary: ECP5 SerDes Out-Of-Band Tx/Rx

Documentation

USB3 LFPS Using ECP5 SerDes I/O